M24L416256DA-70TEG 参数 Datasheet PDF下载

ESMT

Switching Waveforms (continued)

Write Cycle No. 1(

WE

Controlled)[12, 13, 17, 18, 19]

M24L416256DA

Notes:

17.Data I/O is high impedance if OE > V

IH

.

18.If Chip Enable goes INACTIVE simultaneously with

WE

=HIGH, the output remains in a high-impedance state.

19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jul. 2008

Revision: 1.5

7/15