M24L216128SA-55TEG 参数 Datasheet PDF下载

ESMT

Avoid Timing

M24L216128SA

ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal

shorter than t

RC

during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during

15μs shown as in Avoidable timing 1 or toggle CE to high (≧t

RC

) one time at least shown as in Avoidable Timing 2.

Abnormal Timing

≧15μ

s

CE

WE

＜

t

RC

Address

Avoidable Timing 1

≧15μ

s

CE

WE

≧

t

RC

Address

Avoidable Timing 2

≧15μ

s

CE

≧

t

RC

WE

＜

t

RC

Address

Elite Semiconductor Memory Technology Inc.

Publication Date

:

Jul. 2008

Revision

:

1.2

9/14