ESMT
M24L216128DA
AC Test Loads and Waveforms
Parameters
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
R1
R2
RTH
VTH
Switching Characteristics Over the Operating Range[10]
-55 [14]
Min.
-70
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
Description
Unit
Max.
Min.
70
Max.
Read Cycle Time
55[14]
5
ns
ns
ns
ns
Address to Data Valid
Data Hold from Address Change
55
70
10
55
25
70
35
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
tDOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
5
2
5
5
OE LOW to LOW Z[11, 12]
25
25
OE HIGH to High Z[11, 12]
CE1 LOW and CE2 HIGH to Low Z[11, 12]
CE1 HIGH and CE2 LOW to High Z[11, 12]
BLE /BHE LOW to Data Valid
25
55
25
70
tLZBE
tHZBE
5
5
BLE /BHE LOW to Low Z[11, 12]
10
0
25
10
BLE /BHE HIGH to High Z[11, 12]
Address Skew
tSK[14]
Write Cycle[12]
tWC
Write Cycle Time
55
45
70
55
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
tAW
tHA
tSA
45
0
0
55
0
0
ns
ns
ns
Notes:
10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V
to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of WE , CE1 = VIL, CE2 = VIH, BHE and/or BLE = VIL.
All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data
input set-up and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be Chip-enable controlled. In this case tACE is the critical parameter
and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must
be stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2 5/14
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
