ESMT
M24L16161ZA
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 19, 22, 23]
Truth Table[24, 25]
Inputs/Outputs
High Z
High Z
High Z
Mode
Power
CE
H
X
OE
X
X
ZZ
H
H
WE
X
X
BHE
X
H
BLE
X
H
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
H
L
X
X
H
H
H
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Read
Read
Active (ICC
)
Data Out (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
H
L
H
L
H
L
Active (ICC
)
H
L
H
L
L
H
Active (ICC
)
H
H
H
L
L
L
H
H
H
H
H
H
L
H
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Active (ICC
Active (ICC
Active (ICC
)
)
)
H
Write (Upper Byte and Lower
Byte)
H
L
L
L
L
L
L
L
L
H
L
L
L
L
X
X
X
X
X
X
L
H
L
L
L
Data In (I/O0–I/O15)
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
Data In (I/O0–I/O7);
(I/O8–I/O15) in High Z
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z
Write (Lower Byte Only)
Write (Upper Byte Only)
H
L
Write (Variable Address Mode
Register)
L
Data In (A0–A4)
High Z
X
X
Deep Power-down/PAR
Deep Sleep (IZZ)/Standb
Notes:
24.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
25.During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0 13/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
