ESMT
M13S64164A
Power up & Initialization Sequence
11
12
13
15
17
19
20
1
2
3
9
10
14
16
18
6
8
4
5
7
0
C L K
C L K
H i g h l e v e l i s r e q u i r e d
C K E
C S
R A S
C A S
W E
B A 0
BA1 ,A9,A11
A 1 0 / A P
A8
A7
A D D R E S S K E Y
A 1 ~ A 6
A0
M i n i m u m 2 0 0 C y cl e
H i g h - Z
D Q
t
R P
t
M R D
t
R C
t
R C
Mi n i m u m o f
2 R e f re sh Cyc l e s a r e r e q u i r e d
H i g h - Z
D Q S
P re ch a r g e
A l l B a n k
EMRS
DL L E na b le
A n y
C o m m a n d
P r e ch a r g e
A l l B a n k
(Power & Clock must be
stable for 2 0 0 u s
before precharge
All Bank)
2 n d A u t o R e f r e sh
Mo de R e s i st e r S e t
1 s t Au t o Re f re s h
M RS
D L L Re se t
:
D o n ' t C a r e
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4 43/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
