ESMT
M13S64164A
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from
the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
NOP
R EAD A
N OP
NO P
N OP
N OP
NO P
CO M M AND
NO P
N OP
D QS
C AS L a t en c y =3
D o u t0 Do u t 1 D o u t2
DQ' s
D o u t3
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge
enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C L K
C L K
NO P
NO P
W R I T E
NO P
NO P
NO P
NO P
NO P
NO P
C O M M A N D
t D S H
tD S S
tD Q S S
tW P S T
DQ S
tW P R E S
D i n 2 D i n 3
D i n 1
D i n 0
D Q ' s
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4 15/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
