ESMT
IDD Specifications
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
150
40
40
15
70
130
120
70
Version
-4
75
85
-5
65
75
8
35
35
15
60
120
110
60
3
130
M13S64164A (2Y)
-6
55
65
Unit
mA
mA
mA
30
30
15
50
110
100
50
mA
mA
mA
mA
mA
mA
mA
mA
110
mA
Input / Output Capacitance
Parameter
Input capacitance (A0~A11, BA0~BA1,
CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Package
TSOP
BGA
TSOP
BGA
TSOP
BGA
TSOP
BGA
Symbol
C
IN1
Min
2
TBD
2
TBD
2
TBD
2
TBD
Max
4
TBD
4
TBD
6
TBD
4
TBD
Delta Cap
(max)
0.5
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Note
1,4
C
IN2
0.25
1,4
C
OUT
0.5
1,2,3,4
Input capacitance (DM)
C
IN3
0.5
1,2,3,4
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. For all devices, V
DDQ
= 2.5V
±
0.2V, V
DD
= 2.5V
±
0.2V. f=100MHz, T
A
=25°C, V
OUT
(DC) =
V
DDQ
/2, V
OUT
(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in
loading (to facilitate trace matching at the board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2012
Revision : 1.0
7/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
