ESMT
M13S64164A (2Y)
Command Truth Table
BA0,
BA1
A11,
A9~A0
COMMAND
CKEn-1 CKEn
DM
A10/AP
Note
CS RAS CAS
WE
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
X
X
OP CODE
OP CODE
1,2
1,2
3
H
L
L
L
H
X
X
X
Entry
L
H
X
3
3
3
Refresh
Self Refresh
L
H
L
H
X
L
H
X
H
H
X
H
Exit
L
X
X
Bank Active & Row Addr.
H
V
V
Row Address
Read &
Column
Address
Column
Address
(A0 ~ A7)
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
H
H
X
X
L
L
H
H
L
L
H
L
X
V
Write &
Column
Address
Column
Address
(A0 ~ A7)
4,8
V
H
4,6,8
7
Burst Terminate
Bank Selection
All Banks
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
V
X
L
Precharge
X
H
5
H
L
X
H
X
X
H
X
H
X
H
X
H
X
X
H
X
H
X
H
X
H
X
X
H
X
H
X
H
Entry
H
L
L
H
L
X
X
X
Active Power Down Mode
X
Exit
X
H
L
Entry
H
Precharge Power Down
Mode
X
X
H
L
Exit
L
H
X
X
X
Deselect (NOP)
H
L
H
No Operation (NOP)
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Notes:
1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst Terminate command is valid at every burst length.
8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding
and coincident DM is “High”. (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2012
Revision : 1.0 12/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
