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M13S5121632A 参数 Datasheet PDF下载

M13S5121632A图片预览
型号: M13S5121632A
PDF下载: 下载PDF文件 查看货源
内容描述: 8M ×16位×4银行双倍数据速率SDRAM [8M x 16 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 47 页 / 966 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S5121632A  
AC Operating Test Conditions  
Parameter  
Value  
Unit  
Input reference voltage for clock (VREF  
Input signal maximum peak swing  
Input signal minimum slew rate  
Input levels (VIH/VIL)  
)
0.5*VDDQ  
V
V
1.5  
1.0  
V/ns  
V
VREF+0.31/VREF-0.31  
Input timing measurement reference level  
Output timing reference level  
VREF  
VTT  
V
V
AC Timing Parameter & Specifications  
(VDD = 2.5V~2.7V, VDDQ= 2.5V~2.7V, TA =0°C ~ 70°C )  
-5  
Unit  
Note  
Parameter  
Symbol  
min  
7.5  
max  
13  
CL2  
CL2.5  
CL3  
Clock Period  
tCK  
ns  
ns  
6.0  
13  
5.0  
10  
tAC  
-0.7  
+0.7  
Access time from CLK/ CLK  
CLK high-level width  
tCH  
tCL  
0.45  
0.45  
-0.6  
0.75  
0.5  
0.55  
0.55  
+0.6  
1.25  
-
tCK  
tCK  
ns  
tCK  
ns  
ns  
CLK low-level width  
Data strobe edge to clock edge  
tDQSCK  
tDQSS  
tDS  
Clock to first rising edge of DQS delay  
Data-in and DM setup time (to DQS)  
Data-in and DM hold time (to DQS)  
tDH  
0.5  
-
DQ and DM input pulse width (for each  
input)  
tDIPW  
1.75  
-
ns  
Input setup time  
tIS  
0.9  
0.9  
0.35  
0.35  
0.2  
0.2  
-
-
ns  
ns  
tCK  
tCK  
tCK  
tCK  
ns  
5
5
Input hold time  
tIH  
-
DQS input high pulse width  
DQS input low pulse width  
DQS falling edge to CLK rising-setup time  
DQS falling edge from CLK rising-hold time  
Data strobe edge to output data edge  
tDQSH  
tDQSL  
tDSS  
tDSH  
tDQSQ  
-
-
-
-
0.40  
Data-out high-impedance window from  
CLK/ CLK  
tHZ  
-0.7  
-0.7  
+0.7  
+0.7  
ns  
ns  
1
1
Data-out low-impedance window from  
CLK/ CLK  
tLZ  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Oct. 2008  
Revision : 1.0 6/47