ESMT
M13S5121632A
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
0
1
2
3
4
5
6
7
8
C L K
C L K
NO P
NO P
NO P
NO P
NO P
NO P
W R I T E
NO P
NO P
C O M M A N D
tD Q S S
DQ S
Din 4 Din 5
Din 3
Din 0 Din 1 Din 2
Din 6 Din 7
D Q ' s
D M
masked by DM = H
Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be
delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
CO M M A ND
Re a d
Au to Pre ch arg e
A
B a nk
A
NO P
NO P
NOP
NO P
NO P
NOP
NO P
AC T I VE
D QS
C A S L a t e n cy = 3
Dout 2 Dout 3
Dout 0 Dout 1
DQ ' s
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0 23/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
