欢迎访问ic37.com |
会员登录 免费注册
发布采购

M13S5121632A-4TG2R 参数 Datasheet PDF下载

M13S5121632A-4TG2R图片预览
型号: M13S5121632A-4TG2R
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 48 页 / 666 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第17页浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第18页浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第19页浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第20页浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第22页浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第23页浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第24页浏览型号M13S5121632A-4TG2R的Datasheet PDF文件第25页  
ESMT  
M13S5121632A (2R)  
Write Interrupted by a Write  
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the  
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining  
addresses are overridden by the new address and data will be written into the device until the programmed burst length is  
satisfied.  
<Burst Length = 4>  
0
1
2
3
4
5
6
7
8
C L K  
C L K  
1
t C K  
W RITE A  
W RITE B  
NO P  
NO P  
NO P  
N O P  
CO MMA ND  
N OP  
N OP  
N OP  
Hi - Z  
Hi- Z  
DQ S  
DIN A0  
DIN A1  
DIN B0  
DIN B1  
DIN B2  
DIN B3  
DQ ' s  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Feb. 2013  
Revision : 1.3 21/48  
 复制成功!