ESMT
M13S5121632A (2R)
Burst Address Ordering for Burst Length
Burst
Starting
Sequential Mode
Interleave Mode
Length
Address (A2, A1, A0)
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
0, 1
0, 1
2
4
1, 0
1, 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning
to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode,
the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command
can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support reduced drive
strength options, intended for lighter load and/or point-to-point environments.
Mode Register
0
1
2
3
4
5
6
7
C L K
C L K
* 1
A n y
C o m m a n d
P r e c h a r g e
A l l B a n k s
M R S
/
E M R S
C O M M A N D
* 2
R P
t
C K
t
t
M R D
*1: MRS/EMRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS/EMRS command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2013
Revision : 1.3 16/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
