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M13S2561616A-5BG 参数 Datasheet PDF下载

M13S2561616A-5BG图片预览
型号: M13S2561616A-5BG
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ×16位×4银行双倍数据速率SDRAM [4M x 16 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 49 页 / 1315 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DC Specifications
Parameter
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down
Standby Current
Idle Standby Current
Active Power-down
Standby Current
Active Standby Current
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
Operation Current
(Four Bank Operation)
Symbol
Test Condition
t
RC
= t
RC
(min), t
CK
= t
CK
(min)
Active – Precharge
Burst Length = 2, t
RC
= t
RC
(min), CL= 2.5,
I
OUT
= 0mA, Active-Read- Precharge
CKE
V
IL
(max), t
CK
= t
CK
(min), All banks idle
CKE
V
IH
(min), CS
V
IH
(min), t
CK
= t
CK
(min)
All banks ACT, CKE
V
IL
(max), t
CK
= t
CK
(min)
One bank; Active-Precharge, t
RC
= t
RAS
(max),
t
CK
= t
CK
(min)
Burst Length = 2, CL= 2.5 , t
CK
= t
CK
(min),
I
OUT
= 0mA
Burst Length = 2, CL= 2.5 , t
CK
= t
CK
(min)
t
RC
t
RFC
(min)
CKE
0.2V
Four bank interleaving with BL = 4, t
RC
= t
RC
(min),
burst mode; Read with auto precharge;
Address and control input on NOP edge are not
changing. I
OUT
= 0mA
-4
M13S2561616A
Version
-5
130
185
30
60
50
95
290
290
270
5
300
-6
120
165
25
55
45
90
250
250
250
5
270
Unit Note
IDD0
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
140
190
40
70
55
120
300
300
300
6
350
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
Note: 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note: 1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V
DD
= 2.3V~2.7V, V
DDQ
=2.3V~2.7V, T
A
= 25 °C , f = 1MHz)
(V
DD
= 2.4V~2.8V, V
DDQ
= 2.4V~2.8V, T
A
= 25 °C , f = 1MHz (only for speed -4))
Parameter
Input capacitance
(A0~A12, BA0~BA1, CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
C
IN1
C
IN2
C
OUT
C
IN3
2.0
2.0
4.0
4.0
3.0
3.0
5.0
5.0
pF
pF
pF
pF
Symbol
Min
Max
Unit
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2009
Revision : 2.0
5/49