ESMT
M13S2561616A
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not
defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode
register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A12 and BA1 in
the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set
to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
RFU : Must be set “0”
D.I.C DLL
Output Driver Strength Control
A0
0
DLL Enable
Enable
0
1
Normal
Weak
1
Disable
BA1 BA0
Operaing Mode
MRS Cycle
0
0
0
1
EMRS Cycle
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2009
Revision : 2.0 12/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
