ESMT
DDR SDRAM
Features
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Four bank operation
CAS Latency : 2, 2.5, 3, 4
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
M13S2561616A (2K)
4M x 16 Bit x 4 Banks
Double Data Rate SDRAM
All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Data mask (DM) for write masking only
V
DD
= 2.5V
±
0.2V, V
DDQ
= 2.5V
±
0.2V
V
DD
= 2.6V
±
0.2V, V
DDQ
= 2.6V
±
0.2V (for speed grade -4)
7.8us refresh interval
Auto & Self refresh
2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
M13S2561616A -4TG2K
M13S2561616A -5TG2K
M13S2561616A -6TG2K
M13S2561616A -4BG2K
M13S2561616A -5BG2K
M13S2561616A -6BG2K
Max Freq.
250MHz (DDR500)
200MHz (DDR400)
166MHz (DDR333)
250MHz (DDR500)
200MHz (DDR400)
166MHz (DDR333)
V
DD
2.6V
2.5V
2.6V
2.5V
60 Ball BGA
66 pin TSOPII
Pb-free
Package
Comments
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2011
Revision : 1.6
1/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
