ESMT
M13S2561616A (2K)
Operation Temperature Condition -40°C~85°C
AC Timing Parameter & Specifications – continued
-5
-6
Parameter
Write recovery time
Symbol
Unit
Note
min
15
2
max
min
15
2
max
tWR
tWTR
ns
tCK
us
tCK
tCK
tCK
tCK
ns
tCK
tCK
ns
Write data in to Read command delay
Average periodic refresh interval
Write preamble
tREFI
7.8
7.8
14
12
tWPRE
tWPST
tRPRE
tRPST
tWPRES
tMRD
0.25
0.4
0.9
0.4
0
0.25
0.4
0.9
0.4
0
Write postamble
0.6
1.1
0.6
0.6
1.1
0.6
Read preamble
Read postamble
Clock to DQS write preamble setup time
Mode Register Set command cycle time
Exit self refresh to Read command
Exit self refresh to non-Read command
13
23
1
2
tXSRD
tXSNR
200
75
200
75
(tWR/tCK
)
(tWR/tCK
)
Auto Precharge write recovery+precharge time
tDAL
+
+
tCK
(tRP/tCK
)
(tRP/tCK)
Notes:
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the
range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively
switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤
0.2VDDQ is recognized as LOW.
7. Enables on-chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CLK/ CLK input reference level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross;
the input reference level for signals other than CLK/ CLK , is VREF
.
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2010
Revision : 1.2 10/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
