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M13S128324A-5BG 参数 Datasheet PDF下载

M13S128324A-5BG图片预览
型号: M13S128324A-5BG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行双倍数据速率SDRAM [1M x 32 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 50 页 / 950 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S128324A  
Precharge  
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when  
CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to  
precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which  
bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command  
can be issued. After tRP from the precharge, an active command to the same bank can be initiated.  
Burst Selection for Precharge by Bank address bits  
A8/AP  
BA1  
0
BA0  
0
Precharge  
Bank A Only  
Bank B Only  
Bank C Only  
Bank D Only  
All Banks  
0
0
0
0
1
0
1
1
0
1
1
X
X
NOP & Device Deselect  
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control  
inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both  
Deselect and NOP the device should finish the current operation when this command is issued.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jul. 2009  
Revision : 2.3 13/50