ESMT
M13S128324A (2M)
AC Timing Parameter & Specifications - continued
-3.6
-4
-5
-6
Symbol
Unit
Note
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Active to Precharge command
tRAS
tRC
39.6
70K
40
70K
40
70K
42
70K
ns
ns
Active to Active /Auto Refresh
command period
54
52
68
55
70
60
72
Auto Refresh to Active /Auto Refresh
command period
tRFC
64.8
ns
Active to Read delay
tRCDRD
tRCDWR
tRP
14.4
10
15
10
15
15
10
18
18
18
ns
ns
ns
Active to Write delay
Precharge command period
14.4
15
Active to Read with Auto Precharge
command
tRCDRD or
t
t
RCDRD or
RAS min
t
t
RCDRD or
RAS min
tRCDRD or
tRAP
tRRD
ns
ns
t
RAS min
t
RAS min
Active bank A to Active bank B
command
10
10
10
12
Write recovery time
tWR
tWTR
15
2
15
2
15
2
15
2
ns
tCK
tCK
us
Write data in to Read command delay
Col. Address to Col. Address delay
Average periodic refresh interval
Write preamble
tCCD
1
1
1
1
tREFI
tWPRE
tWPST
tRPRE
tRPST
7.8
7.8
7.8
7.8
14
12
0.25
0.4
0.9
0.4
0.25
0.4
0.9
0.4
0.25
0.4
0.9
0.4
0.25
0.4
0.9
0.4
tCK
tCK
tCK
tCK
Write postamble
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
0.6
Read preamble
Read postamble
Clock to DQS write preamble setup
time
tWPRES
0
0
0
0
ns
13
Mode Register Set command cycle
time
tMRD
tXSRD
tXSNR
2
2
2
2
tCK
tCK
ns
Exit self refresh to Read command
200
75
200
75
200
75
200
75
Exit self refresh to non-Read
command
(tWR/tCK
)
(tWR/tCK
)
Auto Precharge write recovery +
precharge time
(tWR/tCK
+(tRP/tCK
)
)
(tWR/tCK
+(tRP/tCK
)
)
tDAL
tCK
23
+(tRP/tCK
)
+(tRP/tCK
)
Notes:
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not
intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference
load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial
transmission line terminated at the tester electronics).
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3 10/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
