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M13S128168A-5TG 参数 Datasheet PDF下载

M13S128168A-5TG图片预览
型号: M13S128168A-5TG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4银行双倍数据速率SDRAM [2M x 16 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 49 页 / 1492 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S128168A  
Basic Functionality  
Power-Up and Initialization Sequence  
The following sequence is required for POWER UP and Initialization.  
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)  
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Apply VDD before or at the same time as VDDQ.  
Apply VDDQ before or at the same time as VTT & VREF).  
2. Start clock and maintain stable condition for a minimun of 200us.  
3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high.  
4. Issue precharge commands for all banks of the device.  
*1 5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the  
rest address pins, A1~A11 and BA1)  
*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.  
(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)  
*2 7. Issue precharge commands for all banks of the device.  
8. Issue 2 or more auto-refresh commands.  
9. Issue a mode register set command with low to A8 to initialize device operation.  
*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional  
200 cycles of clock input is required to lock the DLL after enabling DLL.  
*2 Sequence of 6 & 7 is regardless of the order.  
Power up & Initialization Sequence  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
C L K  
C L K  
tR F C  
tR P  
tR P  
tR F C  
C o m m a n d  
A
n y  
M R S  
D l l R e s e t  
Mode  
Register Set  
p r e c ha r g e  
A l l B a n k s  
p r e c ha r g e  
A l l B a n k s  
1 s t A u t o  
Re f r e s h  
2 n d A u t o  
Re f r e s h  
EMRS  
C o m m a n d  
m i n . 2 0 0 C y c l e  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2007  
Revision : 1.8 10/49