ESMT
IDD Parameters and Test Conditions
Test Condition
M13S128168A (2N)
Symbol
IDD0
Note
Operating Current (one bank Active - Precharge):
t
RC
= t
RC
(min); t
CK
= t
CK
(min); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles; CS = high between valid commands.
Operating Current (one bank Active - Read - Precharge):
One bank open; BL = 4; t
RC
= t
RC
(min); t
CK
= t
CK
(min); I
OUT
= 0mA;
Address and control inputs changing once per deselect cycle; CS = high between valid commands
Precharge Power-down Standby Current:
All banks idle; Power-down mode; t
CK
= t
CK
(min); CKE
V
IL
(max); V
IN
= V
REF
for DQ, DQS and DM.
Precharge Floating Standby Current:
CS
V
IH
(min); All banks idle; CKE
V
IH
(min); t
CK
= t
CK
(min);
Address and other control inputs changing once per clock cycle; V
IN
= V
REF
for DQ, DQS, and DM.
Precharge Quiet Standby Current:
CS
V
IH
(min); All banks idle; CKE
V
IH
(min); t
CK
= t
CK
(min);
Address and other control inputs stable at
V
IH
(min) or
V
IL
(max); V
IN
= V
REF
for DQ, DQS, and DM.
Active Power-down Standby Current:
One bank active; Power-down mode; CKE
V
IL
(max); t
CK
= t
CK
(min); V
IN
= V
REF
for DQ, DQS, and DM.
Active Standby Current:
CS
V
IH
(min); CKE
V
IH
(min); One bank active; t
RC
= t
RAS
(max); t
CK
= t
CK
(min);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle.
Operating Current (burst read):
BL = 2; Continuous burst reads; One bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(min); I
OUT
= 0mA;
50% of data changing on every transfer.
Operating Current (burst write):
BL = 2; Continuous burst writes; One bank active;
Address and control inputs changing once per clock cycle; t
CK
= t
CK
(min);
DQ, DM, and DQS inputs changing twice per clock cycle; 50% of input data changing at every transfer.
Auto Refresh Current:
t
RC
= t
RFC
(min)
Self Refresh Current:
CKE
0.2V; external clock on; t
CK
= t
CK
(min)
Operating Current (Four bank operation):
Four-bank interleaving READs (burst = 4) with auto precharge; t
RC
= t
RC
(min); t
CK
= t
CK
(min);
Address and control inputs change only during ACTIVE, READ, or WRITE commands; I
OUT
= 0mA.
Notes:
1. Enable on-chip refresh and address counters.
2. Random address is changing; 50% of data is changing at every transfer.
IDD1
2
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
1
IDD7
2
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2013
Revision : 1.2
6/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
