ESMT
M13S128168A (2N)
Automotive Grade
AC Timing Parameter & Specifications – continued
-4
-5
-6
Parameter
Symbol
Unit
Note
min
max
min
max
min
max
Active to Precharge command
tRAS
tRC
36
70K
40
70K
42
70K
ns
ns
Active to Active /Auto Refresh
command period
52
60
55
70
60
72
Auto Refresh to Active / Auto Refresh
command period
tRFC
ns
Active to Read, Write delay
Precharge command period
tRCD
tRP
16
16
15
15
18
18
ns
ns
Active to Read with Auto Precharge
command
tRAP
tRRD
16
8
15
10
18
12
ns
ns
Active bank A to Active bank B
command
Write recovery time
tWR
15
2
15
2
15
2
ns
Write data in to Read command delay
tWTR
tCK
Average periodic refresh interval for
TA 85℃
tREFI
15.6
3.9
15.6
3.9
15.6
3.9
us
us
14
14
Average periodic refresh interval for TA
>85℃ (VA grade only)
tREFI
Write preamble
Write postamble
Read preamble
Read postamble
tWPRE
tWPST
tRPRE
tRPST
0.25
0.4
0.9
0.4
0.25
0.4
0.9
0.4
0.25
0.4
0.9
0.4
tCK
tCK
tCK
tCK
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
0.6
12
13
Clock to DQS write preamble setup
time
tWPRES
0
0
0
ns
Mode Register Set command cycle
time
tMRD
tXSRD
tXSNR
2
2
2
tCK
tCK
ns
Exit self refresh to Read command
200
75
200
75
200
75
Exit self refresh to non-Read
command
(tWR/tCK
)
(tWR/tCK
)
(tWR/tCK
)
Auto Precharge write recovery +
precharge time
tDAL
+
+
+
tCK
23
(tRP/tCK
)
(tRP/tCK
)
(tRP/tCK)
Notes:
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.1 10/49