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M12S64164A-7TG 参数 Datasheet PDF下载

M12S64164A-7TG图片预览
型号: M12S64164A-7TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位×4银行同步DRAM [1M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器
文件页数/大小: 45 页 / 1058 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC CHARACTERISTICS
(AC operating condition unless otherwise noted)
PARAMATER
CAS latency = 3
CAS latency = 2
CLK to valid
output delay
Output data
hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
Note:
CAS latency = 3
t
SHZ
CAS latency = 2
6
6
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SAC
2.5
2.5
2.5
2.5
1.5
1
0
5.5
SYMBOL
-6
MIN
6
10
5.5
6
2.5
2.5
2.5
2.5
1.5
1
0
6
MAX
1000
MIN
7
10
6
6
2.5
2.5
3
3
2.5
1.5
0
-7
MAX
1000
MIN
10
12
-10
M12S64164A
MAX
1000
7
8
UNIT
NOTE
CLK cycle time
t
CC
ns
1
ns
1,2
ns
ns
ns
ns
ns
ns
7
ns
8
2
3
3
3
3
2
-
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
6/45