ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T
A
= 0 to 70
°
C
PARAMETER
Operating Current
(One Bank Active)
SYMBOL
TEST CONDITION
Burst Length = 1, t
RC
≥
t
RC
(min), I
OL
= 0 mA,
tcc = tcc(min)
CKE
≤
V
IL
(max), tcc = tcc(min)
CKE & CLK
≤
V
IL
(max), tcc =
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), tcc = tcc(min)
Input signals are changed one time during 2CLK
CKE
≥
V
IH
(min), CLK
≤
V
IL(max)
, tcc =
∞
input signals are stable
CKE
≤
V
IL
(max), tcc = tcc(min)
CKE & CLK
≤
V
IL
(max), tcc =
∞
CS CKE
≥
V
IH
(min), CS
≥
V
IH
(min), tcc = 15ns
Input signals are changed one time during 2 CLKs
All other pins
≥
V
DD
- 0.2V or
≤
0.2V
I
CC3NS
I
CC4
I
CC5
I
CC6
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), tcc =
∞
input signals are stable
I
OL
= 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
t
RFC
≥
t
RFC
(min), t
CC
= tcc(min)
CKE
≤
0.2V
150
150
M12S64164A
VERSION
-6
85
-7
85
2
-10
60
UNIT
NOTE
I
CC1
mA
1,2
I
CC2P
Precharge Standby Current
in power-down mode
I
CC2PS
Precharge Standby Current
in non power-down mode
I
CC2N
mA
1
20
mA
10
10
10
30
mA
mA
I
CC2NS
Active Standby Current
in power-down mode
I
CC3P
I
CC3PS
I
CC3N
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note:
25
140
140
1
120
120
mA
mA
mA
mA
1,2
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
4/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
