ESMT
M12S64322A
10. Clock Suspend Exit & Power Down Exit
1 ) C l o c k S u s p e n d ( = Ac t i v e P o w e r D o w n ) E x i t
2 ) P o w e r D o w n ( = P r e c h a r g e P o w e r D o w n )
CLK
CK E
CLK
CK E
tS S
tS S
Inter nal
Internal
CLK
* N o t e 1
* N o t e 2
CLK
C M D
R D
C M D
A C T
NO P
11. Auto Refresh & Self Refresh
* N o t e 3
1 ) A u t o R e f r e s h
&
S e l f R e f r e s h
C L K
* N o t e 4
* N o t e 5
C M D
C M D
P R E
A R
C K E
t R P
t R C
* N o t e 8
2 ) S e l f R e f r e s h
C L K
* N o t e 4
C M D
P R E
S R
C M D
C K E
t R P
t R C
*Note : 1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh (40% cycles) is recommended.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0 24/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
