ESMT
M12S16161A
Operation Temperature Condition -40°C~85°C
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note2
CAa
ADDR
BA
CBb
CAc
RBb
CBd
RAa
A10/AP
DQ
RAa
RBb
DBb3 DAc0 DAc1
DBb2
DAa1 DAa2
DBb0 DBb1
DBd0
DAa0
DAa3
DBd1
tCDL
tRDL
WE
*Note1
DQM
Precharge
(Both Banks)
Row Active
(A-Bank)
Write
(B-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
: Don't care
*Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2007
Revision : 1.0 17/30