ESMT
M12S16161A
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page
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C L O C K
H I G H
C K E
CS
RAS
CAS
A D D R
BA
CA a
CA b
RA a
A10/AP
RA a
*Note2
1
QAa3 QAa4
1
QAa2
QAa1
QAb0
QAb1
QAb0
QAb5
QAb3 QAb4
QAa0
CL = 2
QAa1
QAa0
QAb2
D Q
2
2
QAa2 QAa3 QAa4
CL= 3
WE
QAb4
QAb3
QAb1 QAb2
QAb5
*Note 1
D Q M
Read
( A - Ban k )
Burst Stop
Pre ch arg e
( A- B an k )
Read
(A - Ban k )
Row A c t i ve
( A- B an k )
:D o n' t C a r e
*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.2 20/28
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
