ESMT
M12S16161A
Read & Write Cycle at Same Bank @Burst Length = 4
0
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CLOCK
CKE
HIGH
*Note1
tRC
CS
tRCD
RAS
CAS
*Note2
ADDR
Ra
Rb
Cb0
Ca0
BA
A10/AP
Ra
Rb
tOH
CL=2
CL=3
Qa2
Qa1
Qa3
Db2
Qa0
tSAC
Db1
Db3
Db0
Db0
tRAC
*Note4
QC
tSHZ
Qa3
*Note3
tRDL
tOH
Qa1
Qa0
Qa2
Db2
Db1
Db3
tRAC
*Note3
tSHZ
*Note4
tSAC
tRDL
WE
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
: Don't care
*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.2 13/28
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
