ESMT
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
0.9XV
DDQ
/ 0.2
0.5xV
DDQ
tr/tf = 1/1
0.5xV
DDQ
See Fig. 2
M12S128324A
Unit
V
V
ns
V
AC OPERATING TEST CONDITIONS [
V
DD
= 2.5V
±
0.2V, V
DD
= 2.375V~2.625V (for -6), T
A
= 0 to 70 °C ]
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
@ Operating
@ Auto Refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Symbol
-6
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC(min)
t
RFC(min)
t
CDL(min)
t
RDL(min)
t
BDL(min)
60
75
1
2
1
12
18
18
42
100
70
84
CLK
CLK
CLK
2
2
2
-7
14
18
20
42
ns
ns
ns
ns
us
ns
1
1
1
1
1
Unit
Note
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
6/46