ESMT
M12S128168A
AC OPERATING TEST CONDITIONS (VDD = 2.5V ± 0.2V，TA = 0 to 70°C )
Parameter
Input levels (Vih/Vil)
Value
0.9xVDDQ/0.2
0.5xVDDQ
tr/tf = 1/1
Unit
V
Input timing measurement reference level
Input rise and fall-time
V
ns
V
Output timing measurement reference level
Output load condition
0.5xVDDQ
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-6
12
18
18
-7
14
20
20
-8
20
30
30
Row active to row active delay
tRRD(min)
tRCD(min)
ns
ns
1
1
RAS to CAS delay
Row precharge time
tRP(min)
ns
ns
1
1
tRAS(min)
40
42
100
63
60
Row active time
tRAS(max)
tRC(min)
us
ns
@ Operating
1
58
60
90
Row cycle time
@ Auto refresh tRFC(min)
70
1
100
ns
tCK
tCK
tCK
ms
1,5
2
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
tCDL(min)
tRDL(min)
tBDL(min)
tREF(max)
2
2
1
2
Refresh period (4,096 rows)
64
6
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2008
Revision: 1.1 6/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
