ESMT
Parameter
Col. address to col. address delay
Number of valid
Output data
Symbol
t
CCD(min)
Version
-6
-7
1
2
1
M12S128168A
Unit
t
CK
ea
Note
3
4
-10
CAS latency = 3
CAS latency = 2
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6
μ
s.)
AC CHARACTERISTICS
(AC operating condition unless otherwise noted)
Parameter
CAS latency = 3
CAS latency = 2
CLK to valid
output delay
Output data
hold time
CLK high pulsh width
CLK low pulsh width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
Note :
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
t
SAC
Symbol
MIN
CLK cycle time
t
CC
6
10
-
-
2.5
2.5
2.5
2.5
1.5
1
1
-
-
5.4
6
-
-
-
-
-
-
-
5.4
6
-6
MAX
1000
MIN
7
10
-
-
2.5
2.5
2.5
2.5
1.5
1
1
-
-
5.4
6
-
-
-
-
-
-
-
5.4
6
-7
MAX
100
MIN
10
12
-
-
2.5
2.5
3
3
2.5
1.5
1
-
-
7
8
-
-
-
-
-
-
-
7
8
ns
1,2
-10
MAX
1000
ns
1
Unit
Note
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
ns
ns
ns
ns
ns
ns
ns
2
3
3
3
3
2
-
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2008
Revision: 1.1
7/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
