M12L64322A-6BIG 参数 Datasheet PDF下载

ESMT

M12L64322A

Operation temperature condition -40

°

C ~ 85

°

C

If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.

If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected

If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.

5.During burst read or write with auto precharge. new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

RP

after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but

makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address

Function

BA0~BA1

RFU

A10/AP

RFU

A9

W.B.L

A8

TM

A7

A6

A5

A4

A3

BT

A2

A1

A0

CAS Latency

Burst Length

Test Mode

A8

0

0

1

1

A7

0

1

0

1

Type

Mode Register Set

Reserved

Reserved

Reserved

A6

0

0

0

0

1

1

1

1

CAS Latency

A5

0

0

1

1

0

0

1

1

A4

0

1

0

1

0

1

0

1

Latency

Reserved

Reserved

2

3

Reserved

Reserved

Reserved

Reserved

Burst Type

A3

0

1

Type

Sequential

Interleave

A2

0

0

0

0

1

1

1

1

A1

0

0

1

1

0

0

1

1

Burst Length

A0

0

1

0

1

0

1

0

1

BT = 0

1

2

4

8

BT = 1

1

2

4

8

Write Burst Length

A9

0

1

Length

Burst

Single Bit

Reserved Reserved

Reserved Reserved

Reserved Reserved

Full Page Reserved

Full Page Length : 256

POWER UP SEQUENCE

1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.

2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note :

1. RFU(Reserved for future use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “ Burst Read single Bit Write” function will be enabled.

3. The full column burst (256 bit) is available only at sequential mode of burst type.

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2007

Revision

:

1.2

9/46