ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T
A
= 0 to 70
°
C
PARAMETER
Operating Current
(One Bank Active)
SYMBOL
TEST CONDITION
Burst Length = 1, t
RC
≥
t
RC
(min), I
OL
= 0 mA,
t
CC
= t
CC
(min)
CKE
≤
V
IL
(max), t
CC
= t
CC
(min)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
M12L64164A (2M)
VERSION
-5
100
-6
85
2
1
20
-7
85
UNIT
NOTE
I
CC1
mA
1,2
I
CC2P
Precharge Standby Current
in power-down mode
I
CC2PS
I
CC2N
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
I
CC2NS
I
CC3P
I
CC3PS
mA
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= t
CC
(min)
Input signals are changed one time during 2CLK
input signals are stable
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≤
V
IL
(max), t
CC
= t
CC
(min)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
I
OL
= 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
t
RFC
≥
t
RFC
(min), t
CC
= t
CC
(min)
CKE
≤
0.2V
180
180
mA
10
10
10
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3N
I
CC3NS
30
mA
25
150
150
1
140
140
mA
mA
mA
mA
1,2
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note:
I
CC4
I
CC5
I
CC6
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2012
Revision: 1.6
4/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
