ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Bank B
Row Decoder
M12L32321A
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DQM0~3
Column Decoder
DQ
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A10
BA
RAS
CAS
WE
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Column Address Strobe
Write Enable
Data Input / Output Mask
DQM0~3
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Oct. 2008
Revision
:
1.1
2/28
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
