ESMT
SDRAM
M12L32162A
Operation Temperature Condition -40°C~105°C
1M x 16Bit x 2Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
CAS Latency (1, 2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Auto refresh (Not support self refresh)
16ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M12L32162A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 1,048,576 words by 16
bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Part NO.
M12L32162A-7TVG
M12L32162A-7BVG
MAX Freq.
143MHz
143MHz
PACKAGE COMMENTS
54 Pin
TSOP(II)
54 Ball BGA
Pb-free
Pb-free
PIN CONFIGURATION (TOP VIEW)
54 PIN TSOP(II)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
NC
BA
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S SQ
DQ14
DQ13
V
D DQ
DQ12
DQ11
V
S SQ
DQ10
DQ9
V
D DQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
54 Ball FVBGA(8mmx8mm)
1
A
B
C
D
E
F
G
H
J
V
SS
DQ14
DQ12
2
DQ15
DQ13
DQ11
3
V
SSQ
4
5
6
7
V
DDQ
8
DQ0
DQ2
DQ4
DQ6
9
V
DD
DQ1
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
DQ3
DQ5
DQ10
DQ9
DQ8
NC
CLK
A11
V
SS
V
DD
LDQM
DQ7
WE
CS
A10
V
DD
UDQM
CKE
A9
CAS
BA
A0
A9
RAS
NC
NC
A8
V
SS
A7
A5
A6
A4
A1
A2
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Dec. 2007
Revision
:
1.2
2/28