ESMT
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
CAS Latency =3
CAS Latency =2
Symbol
t
CC
t
SAC
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
2
2
2
2
2
0
6
6
-5.5
Min
5.5
10
1000
6
6
2
2
2
2
2
0
5.5
5.5
Max
Min
6
10
-6
Max
1000
5.5
5.5
2.5
2.5
2.5
2
2
0
Min
7
10
M12L32162A
-7
Max
1000
6
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
2
3
3
3
3
2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in
Hi-Z
CAS Latency =3
CAS latency =2
6
6
ns
*All AC parameters are measured from half to half.
Note:
1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Parameter
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
Symbol
t
SAC
t
OH
t
SHZ
-5.5
Min
Max
5.5
5.5
2
5.5
5.5
Unit
ns
ns
ns
Note
4
4
4
Output data hold time
CLK to output in
Hi-Z
CAS Latency =3
CAS Latency =2
Note:
4. Special condition (Output Load
≤
10 ohm+10 pF)
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Mar. 2009
Revision
:
1.2
6/29
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
