ESMT
M12L32162A
Read & Write Cycle at Same Bank @Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note1
t
RC
CS
t
RCD
RAS
CAS
*Note2
ADDR
Ra
Ra
Rb
Cb0
Ca0
BA
A10/AP
Rb
t
OH
CL=2
CL=3
Qa2
Qa1
Qa3
Qa2
Db2
Qa0
Db1
Db3
Db0
Db0
t
RAC
t
SHZ
*Note4
QC
t
SAC
*Note3
t
RDL
t
OH
Qa1
Qa3
Qa0
Db2
Db1
Db3
t
RAC
t
SHZ
*Note4
t
SAC
*Note3
t
RDL
WE
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
: Don't care
*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2 13/29
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
