ESMT
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V
，T
A
= 0 to 70
°
C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
M12L2561616A (2A)
Unit
V
V
ns
V
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
@ Auto refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Refresh period (8,192 rows)
Number of valid
Output data
Symbol
-5
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
t
REF
(max)
55
55
10
15
15
40
Version
-6
12
18
18
42
100
60
60
1
2
1
1
64
2
1
63
63
-7
14
20
20
45
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ms
ea
1
1,5
2
2
2
3
6
4
1
1
1
1
Unit
Note
Row cycle time
CAS latency = 3
CAS latency = 2
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x7.8
μ
s.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2012
Revision: 1.2
5/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
