ESMT
M12L2561616A (2K)
8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
* N o t e 3
* N o t e 4
C M D
C M D
P R E
S T O P
W R
W R
D 0
t
R D L
D Q M
D Q M
D Q
D Q
D 0
D 1
D 1
M a s k
D 2
D 3
M a s k
D 5
D 4
* N o t e 1
t
B D L
2 ) R e a d B u r s t S t o p ( B L = 4 )
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C LK
* N o t e 5
C M D
C M D
R D
P R E
R D
S T O P
Q 0
* N o t e 2
D Q ( C L 2 )
D Q ( C L 3 )
Q1
Q 0
D Q ( C L 2 )
D Q ( C L 3 )
Q 0
Q1
Q 0
Q2
Q1
Q 3
Q 2
* N o t e 2
Q 1
Q 3
9. MRS
1 ) M o d e R e g i s t e r S e t
CLK
* N o t e 4
C M D
A C T
PR E
M R S
tR P
2 C L K
*Note: 1. tBDL: 1 CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.
3. Write burst is terminated. tBDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM.
6. PRE: All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 21/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
