ESMT
M12L128324A
Operation temperature condition -40°C~85°C
(b) CL = 3 , B L= 4
CLK
R D
W R
D0
i ) C M D
D Q M
D Q
D2
D1
D3
W R
i i ) C M D
R D
D Q M
D Q
D2
D3
D0
D1
i i i ) C M D
W R
R D
D Q M
D Q
D2
D0
D1
D3
i v ) C M D
W R
R D
D Q M
D Q
H i - Z
D2
D3
D0
D1
v ) C M D
R D
W R
D Q M
D Q
H i - Z
Q0
D0
D1
D2
D3
* N o t e 1
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
1 ) N o r m a l W r i t e ( B L = 4 )
CLK
* N o t e 3
C M D
D Q M
D Q
W R
D0
PR E
* N o t e 2
D3
D1
D2
Ma s k e d b y D Q M
tRDL(min)
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1 23/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
