欢迎访问ic37.com |
会员登录 免费注册
发布采购

M12L128168A-7BG 参数 Datasheet PDF下载

M12L128168A-7BG图片预览
型号: M12L128168A-7BG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4银行同步DRAM [2M x 16 Bit x 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 45 页 / 668 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号M12L128168A-7BG的Datasheet PDF文件第34页浏览型号M12L128168A-7BG的Datasheet PDF文件第35页浏览型号M12L128168A-7BG的Datasheet PDF文件第36页浏览型号M12L128168A-7BG的Datasheet PDF文件第37页浏览型号M12L128168A-7BG的Datasheet PDF文件第39页浏览型号M12L128168A-7BG的Datasheet PDF文件第40页浏览型号M12L128168A-7BG的Datasheet PDF文件第41页浏览型号M12L128168A-7BG的Datasheet PDF文件第42页  
ESMT  
M12L128168A  
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page  
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by  
AC parameter of tRDL  
.
DQM at write interrupted by precharge command is needed to prevent invalid write.  
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input  
data after Row precharge cycle will be masked internally.  
2. Burst stop is valid at every burst length.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Mar. 2009  
Revision: 2.3 38/45  
 复制成功!