ESMT
M12L128168A
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ,TA = 0 to 70°C )
Parameter
Input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall-time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
Vtt = 1.4V
3.3V
50 Ω
1200
Ω
VOH (DC) =2.4V , IOH = -2 mA
VOL (DC) =0.4V , IOL = 2 mA
Output
Output
Z0 =50 Ω
50pF
50pF
870 Ω
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-5
10
15
15
-6
12
18
18
-7
14
20
20
Row active to row active delay
tRRD(min)
tRCD(min)
ns
ns
1
1
RAS to CAS delay
Row precharge time
tRP(min)
ns
ns
1
1
tRAS(min)
38
40
42
Row active time
tRAS(max)
tRC(min)
100
58
us
ns
@ Operating
1
53
55
63
70
Row cycle time
@ Auto refresh tRFC(min)
60
ns
tCK
tCK
tCK
ms
1,5
2
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
tCDL(min)
tRDL(min)
tBDL(min)
tBEF(max)
1
2
2
1
2
Refresh period (4,096 rows)
64
6
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3 5/45