ESMT
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register set
Auto Refresh
Refresh
Self
Refresh
Entry
Exit
(Preliminary)
M12L128324A (2E)
CKEn-1 CKEn
H
H
X
H
L
H
X
X
CS RAS CAS
L
L
L
H
L
L
L
L
H
X
L
H
L
L
H
X
H
L
WE
DQM BA0,1 A10/AP
X
X
X
X
X
X
V
V
OP CODE
X
A11,
A9~A0
Note
1,2
3
3
3
3
L
H
H
X
H
H
L
H
H
X
Row Address
L
H
L
H
X
V
X
L
H
X
Column
Address
(A0~A7)
Column
Address
(A0~A7)
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
4
4,5
4
4,5
6
H
H
H
X
X
X
L
H
L
H
L
L
L
H
L
X
H
L
H
L
H
L
H
H
L
X
H
X
X
H
X
H
X
X
H
L
H
H
X
H
X
X
H
X
H
X
H
L
L
L
X
H
X
X
H
X
H
X
H
X
X
X
X
X
X
V
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Bank Selection
All Banks
Entry
Exit
Entry
Precharge Power Down Mode
Exit
DQM
No Operating Command
H
L
H
L
H
H
X
X
X
V
X
X
X
7
X
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
Note:
1.OP Code: Operating Code
A0~A11 & BA0~BA1: Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1: Bank select addresses.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
7/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
