ESMT
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
(Preliminary)
M12L128324A (2E)
Unit
V
V
ns
V
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V
，T
A
= 0 to 70 °C )
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Vtt = 1.4V
3.3V
1200
Output
870
Ω
30pF
Ω
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
Z0 =50
50
Ω
Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
@ Operating
@ Auto Refresh
Symbol
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
60
60
-5
10
15
15
40
-6
12
18
18
42
100
60
60
1
2
1
1
2
ea
CAS latency = 2
1
4
63
63
-7
14
21
21
42
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
1
1, 5
2
2
2
3
Note
1
1
1
1
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid
Output data
CAS latency = 3
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1
5/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
