ESMT
3. CAS Interrupt (I)
M12L128168A
* N o t e 1
1 )R e a d i n t e r ru p t e d b y R e a d (B L =4 )
CL K
C MD
R D
A
R D
B
AD D
DQ (C L 2 )
D Q( CL 3 )
QA0
QB1 QB2 QB3
QB1 QB2 QB3
QB0
QA0 QB0
t C CD
* N o t e
2
2 ) W r i t e i n t e r r u p t e d b y W ri t e (B L = 2 )
3 ) W r i t e in t e r ru p t e d b y R e a d (B L = 2 )
C L K
C MD
WR
WR
W R
R D
tC CD * N o t e
2
t CC D * No t e
2
A
ADD
D Q
A
B
B
DQ (C L 2 )
D Q( CL 3 )
D B1
DB0
D A0 DB0 D B1
tC D L
D A0
DA0
D B0
* No t e
3
D B1
tC D L
* No t e
3
*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 17/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
