ESMT
M12L128168A
BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Bank D
Bank C
Bank B
Row
Address
Address
Buffer
&
Bank A
Mode
Register
Refresh
Counter
Sense Amplifier
Column Decoder
L(U)DQM
DQ
Column
Address
Buffer
&
CS
RAS
CAS
WE
Data Control Circuit
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
Chip Select
inputs except CLK , CKE and L(U)DQM
CS
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
CKE
Clock Enable
Address
A0 ~ A11
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
A12 , A13
RAS
Bank Select Address
Row Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Enables write operation and row precharge.
Column Address Strobe
Write Enable
CAS
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
L(U)DQM
Data Input / Output Mask
DQ0 ~ DQ15
VDD / VSS
Data Input / Output
Power Supply / Ground
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
VDDQ / VSSQ
N.C
Data Output Power / Ground
No Connection
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0
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