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M12L128168A-7TIG2L 参数 Datasheet PDF下载

M12L128168A-7TIG2L图片预览
型号: M12L128168A-7TIG2L
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 45 页 / 689 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12L128168A (2L)  
Operation Temperature Condition -40°C~85°C  
COMMANDS  
Mode register set command  
( CS ,RAS , CAS , WE = Low)  
The M12L128168A has a mode register that defines how the device operates. In  
this command, A0~A11 and BA0~BA1 are the data input pins. After power on, the  
mode register set command must be executed to initialize the device.  
The mode register can be set only when all banks are in idle state.  
During 2CLK following this command, the M12L128168A cannot accept any  
other commands.  
Activate command  
( CS ,RAS = Low, CAS , WE = High)  
The M12L128168A has four banks, each with 4,096 rows.  
This command activates the bank selected by BA1 and BA0 (BS) and a row  
address selected by A0 through A11.  
This command corresponds to a conventional DRAM’s RAS falling.  
Precharge command  
( CS ,RAS , WE = Low, CAS = High )  
This command begins precharge operation of the bank selected by BA1 and BA0  
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.  
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.  
After this command, the M12L128168A can’t accept the activate command to the  
precharging bank during tRP (precharge to activate command period).  
This command corresponds to a conventional DRAM’s RAS rising.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2012  
Revision: 1.1 13/45