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M12L128168A-6TVAG2N 参数 Datasheet PDF下载

M12L128168A-6TVAG2N图片预览
型号: M12L128168A-6TVAG2N
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 46 页 / 687 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC CHARACTERISTICS
(AC operating condition unless otherwise noted)
Parameter
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
Symbol
MIN
CLK cycle time
CLK to valid
output delay
Output data
hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
Note:
CAS latency = 3
CAS latency = 2
t
CC
5
10
-5
MAX
1000
5
6
2
2
2
2
1.5
0.8
1
4.5
6
2
2
2.5
2.5
1.5
1
1
5.4
6
MIN
6
10
-6
MAX
1000
5.4
6
2
2
M12L128168A (2N)
Automotive Grade
-7
MIN
7
10
MAX
1000
5.4
6
Unit
Note
ns
1
t
SAC
ns
1,2
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
ns
ns
ns
ns
ns
ns
5.4
6
ns
2
3
3
3
3
2
-
2.5
2.5
1.5
1
1
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
7/46