(OLWH07
DRAM
FEATURES
y
y
y
y
y
y
y
y
y
y
M11L416256A/M11L416256SA
256 K x 16 DRAM
EDO PAGE MODE
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ
44 / 40-pin 400mil TSOP (Type II)
X16 organization
EDO (Extended Data-Output) access mode
2
CAS
Byte/Word Read/Write operation
Single 3.3V (
±
10%) power supply
LVTTL-compatible inputs and outputs
512-cycle refresh in 8ms
Refresh modes :
RAS
only,
CAS
BEFORE
RAS
(CBR)
and HIDDEN capabilities
Optional self-refresh capability (S-ver. only)
JEDEC standard pinout
Key AC Parameter
t
RAC
-25
-28
-30
-35
-40
25
28
30
35
40
t
CAC
8
9
9
10
11
t
RC
43
48
55
65
75
t
PC
10
11
12
14
16
PRODUCT NO.
M11L416256A-25J/T
M11L416256A-28J/T
M11L416256A-30J/T
M11L416256A-35J/T
M11L416256A-40J/T
M11L416256SA-25J/T
M11L416256SA-28J/T
M11L416256SA-30J/T
M11L416256SA-35J/T
M11L416256SA-40J/T
Refresh
PACKING
TYPE
Normal
SOJ/TSOPII
Self-Refresh
SOJ/TSOPII
GENERAL DESCRIPTION
The M11L416256 series is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers
Extended Data-Output , 3.3V(
±
10%) single power supply. Access time (-25,-28,-30,-35,-40) , self-refresh and package type
(SOJ, TSOP II) are optional features of this family. All these family have
CAS
- before -
RAS
,
RAS
-only refresh and Hidden
refresh capabilities.
Two access modes are supported by this device: Byte access and Word access. Use only one of the two
CAS
and leave
the other staying high will result in a BYTE access. WORD access happens when two
CAS
(
CASL
,
CASH
) are used.
CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and
CASH
transiting low will
output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
V
C C
I/O0
I/O1
I/O2
I/O3
V
C C
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RA S
NC
A0
A1
A2
A3
V
C C
TSOP (TypeII) Top View
V
S S
I/O1 5
I/O1 4
I/O1 3
I/O1 2
V
S S
I/O1 1
I/O1 0
I/O9
I/O8
NC
CA SL
C ASH
OE
A8
A7
A6
A5
A4
V
SS
V
C C
I/O 0
I/O 1
I/O 2
I/O 3
V
C C
I/O 4
I/O 5
I/O 6
I/O 7
NC
NC
WE
RA S
NC
A0
A1
A2
A3
V
C C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
I/O 11
I/O 10
I/O 9
I/O 8
NC
C AS L
C AS H
OE
A8
A7
A6
A5
A4
V
SS
Elite Memory Technology Inc
Publication Date: Agu. 2001
Revision
:
1.3
1/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
