ESMT
F49L320UA/F49L320BA
Operation Temperature Condition -40°C~85°C
Word mode Secured Silicon Sector Addresses
Sector Address
Sector Size
( x8 )
( x16 )
A20~12
( bytes/words)
Address Range
Address Range
111111111
256/128
3FFF00h-3FFFFFh
1FFF80h-1FFFFFh
Byte mode Secured Silicon Sector Addresses
Sector Address
A20~12
Sector Size
( bytes/words)
( x8 )
Address Range
( x16 )
Address Range
000000000
256/128
000000h-0000FFh
000000h-00007Fh
7.4 More Device Operations
Hardware Data Protection
Logical Inhibit
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware data
protection measures prevent accidental erasure or
programming, which might otherwise be caused by
Write cycles are inhibited by holding any one of
= V ,
OE
IL
CE
is a logical
= V or
IH
WE
= V . To initiate a write cycle,
WE
CE
IH
and
one.
must be a logical zero while
OE
spurious system level signals during V
power-up and
CC
power-down transitions, or from system noise.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
Low VCC Write Inhibit
between its V
and GND.
CC
When V
is less than VLKO, the device does not accept
CC
any write cycles. This protects data during V
power-up
CC
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets.
Power-Up Sequence
The device powers up in the Read Mode. In addition, the
memory contents may only be altered after successful
completion of the predefined command sequences.
Subsequent writes are ignored until V
is greater than
CC
V . The system must provide the proper signals to the
LKO
control pins to prevent unintentional writes when V
is
CC
greater than V
.
LKO
Power-Up Write Inhibit
If
=
= V and
= V during power up, the
OE
IH
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
IL
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on
do not initiate a write cycle.
or
WE
CE
WE
reading array data on power-up.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2008
Revision: 1.1 21/55
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
