ESMT
F49L160UA/F49L160BA
Figure 9. CE Controlled Program Timing Waveform
5 5 5 f o r p r o g r a m P A f o r p r o g r a m
2 A A f o r e r a s e
S A f o r s e c t o r e r a s e
5 5 5 f o r c h i p e r a s e
Data P ol li n g
PA
Addr es s
tW C
tW H
t A S
tA H
W E
OE
tG H E L
tC P
tW H W H 1 o r
2
C E
tC P H
tD H
t W S
tD S
tB U S Y
Dat a
D O U T
DQ7
P D f o r p r o g r a m
3 0 f o r s e c t o r e r a s e
1 0 f o r c h i p e r a s e
A0 f o r p r o g r a m
5 5 f o r e r a s e
tR H
RE S E T
RY/B Y
Notes :
1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device
2. Figure indicates the last two bus cycles of the command sequence..
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.8 30/50
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
